Contract engineering. Hardware and software.
Full-stack web, cloud and mobile apps. Firmware, circuit boards and chips.
Insured: general & professional liability Honolulu, working with teams anywhere
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Hardware
From chip to circuit board.
Mechanical & CAD Mechanical design, sizing and parts.
Feed force measurement device
Bench rig that measures saw feed force.
- RS-775 12 V saw, 6.5 in blade
- NEMA17 + 50:1 planetary feed
- 8 mm lead screw, dual load cells
- ~400 mm printed frame, Arduino
Designed and built
Robot arm
Multi-joint arm, designed in CAD.
- Multi-axis, stepper-driven joints
- Geared reducers at the joints
- 3D-printed structure
Designed
Circuit boards Schematics, layout, power and wireless.
ADC test board
Evaluation board for a custom ADC chip.*
- 4-layer, 105.5 × 83 mm
- 3 V in, dual LDO 1.2 V rails
- Trimmed 0.9 / 0.3 V references, buffered
- QFN-32 socket, buffered clock and reset
Designed and built
48 V motor drive
Field-oriented servo drive for a robot joint.
- 12–58 V bus, 60 A peak (design target)
- 20 A rms continuous (design target)
- STM32G491 + DRV8350S, 1 mΩ shunts
- Ø100 mm, 6-layer, 2× CAN FD
Designed
CAN bus data logger
Vehicle bus logger with cloud upload.
- 2× isolated CAN FD, LIN, 2× UART
- STM32H723, 8 MB PSRAM, microSD
- 6–36 V in, ~5 s hold-up (calculated)
- 120 × 85 mm, 4-layer
Designed
Modular core board
Hub board for a magnetic snap-together kit.
- ESP32-S3, 16 MB flash, 8 MB PSRAM
- 7 magnetic power + data joints
- 5 V bus, 2 A switched
- 58 × 58 mm, 4-layer
Designed
Long-range receiver board
Low-power LoRa receiver with alert sounder.
- nRF52840 + SX1262, 915 MHz LoRa
- ~480 m range (simulated)
- ≥90 dB(A) sounder, 2× AA
- 80 × 48 mm, 4-layer
Designed
Wi-Fi bridge board
Tiny Wi-Fi bridge for a 12 V serial port.
- ESP32-C6, 8 MB flash
- ~11 mA average from 12 V (calculated)
- 15 V-tolerant UART level shifting
- 52 × 22 mm, 2-layer
Designed
Chip design From concept to tapeout.
Fabricated ADC chip
The full die, as taped out and fabricated.
- IHP SG13G2 130 nm, fabricated
- Six ADCs on one die, 32 pads
- Includes the ΔΣ ADC shown next
- Packaged in QFN-32 and measured
Designed and built
Incremental ΔΣ ADC
Second-order incremental delta-sigma ADC.
- IHP SG13G2 130 nm, 1.2 V
- 12-bit target resolution
- Fully differential, MIM capacitors
- Hand-drawn layout in KLayout
Designed and built
Mixed-signal frequency meter chip
On-chip meter for eight ring oscillators.
- IHP SG13G2 130 nm, 1×2 tiles
- 8 rings, 32-bit reciprocal counter
- 50 MHz reference, ÷1 to ÷128 divider
- 2,426 cells, DRC/LVS clean
Designed
Architecture
Eight oscillators, one shared measurement chain.
- Ring select → divider → counter
- Only the reference clock must be accurate
- One 8-bit trim code to every ring
- Registers and statistics over the pins
Designed
Analog oscillator block
Tunable current-starved ring, custom layout.
- 11 stages, 8-bit current DAC
- 2–164 MHz tuning (post-layout simulation)
- ~3× spread over PVT (simulated)
- 91 × 57 µm full-custom macro
Designed
Pre-tapeout verification
Corner, Monte Carlo and post-layout sign-off.
- 45 PVT points (5 × 3 × 3)
- 64-run Monte Carlo
- Post-layout re-simulation
- Monotonic at all 45 PVT points
Simulated
Chip test & bring-up The chip, its test board and the results.
Custom ADC chip
Class chip with six ADCs, in QFN-32.
- IHP SG13G2 130 nm tapeout
- Six teams' ADCs on one die
- Socketed for quick swaps
Designed and built
Test board, assembled
Built, brought up and used on the bench.
- 4 boards fabricated and assembled
- Digilent Analog + Digital Discovery I/O
- On-board references and clock buffer
Designed and built
Measured results
Linear sweeps and noise across six ADCs.
- 0–1.2 V sweep, 50 mV steps
- Clocked at 50, 10 and 2 MHz
- Noise σ 12.3 → 0.42 mV, 50 → 2 MHz
- Automated in Python
Measured
Software
Full stack, cloud and mobile.
Full stack, cloud and mobile Web, iPhone, iPad and Android.
Math Arena
Math games for schools, built for a client.
- 131 games across pre-algebra
- One codebase: web, iPhone, iPad, Android
- Accounts, class leagues, teacher reports
- Cloud hosting and app-store releases
Designed and built
Maxwell Pauly
Engineer · Founder
Born and raised in ‘Ewa Beach (JCHS ’16). BS and MS in electrical and computer engineering from UH Mānoa. Big-tech experience at Amazon Web Services, then years building with small companies and startups. Now bringing that engineering home to local businesses.
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